Is there a JEDEC, EIA or Military standard about optical inspection criteria for chip scale packages?

See if JESD22-B101 addresses it.

Thanks Al, I could sure use this document. But it is not as comprehensive as I thought it would be. I was mainly looking for a standard tolerance of edge chipping on the backside of a chip scale package (i.e. 5 or 10 mils wide or deep for 2mm x 2mm package). One of our customer document referred to "PS 5207 Worldwide Second Optical (Visual I) Inspection Criteria for Mospower Designs & Standard Devices". Maybe I'm not looking hard enough coz I can't find it in the web. Are you familiar with this standard?

Thanks Al, I could sure use this document. But it is not as comprehensive as I thought it would be. I was mainly looking for a standard tolerance of edge chipping on the backside of a chip scale package (i.e. 5 or 10 mils wide or deep for 2mm x 2mm package). One of our customer document referred to "PS 5207 Worldwide Second Optical (Visual I) Inspection Criteria for Mospower Designs & Standard Devices". Maybe I'm not looking hard enough coz I can't find it in the web. Are you familiar with this standard?No, I'm not, but call your customer and ask for the document or where you can get it. If they are imposing it, they should be able to help you.

Carl, look at MIL-STD-883 method 2009.9, external visual inspection for hybrid microcircuits.

Hi Al...I read the standard you attached but it is for a hermetically sealed device which we don't process in our factory...I still downloaded though for future reference.
Also, our customer who referenced the spec that I mentioned is no longer an active customer so I don't think it would be appropriate if I ask them about it now.
Anyway, thanks a lot for your help and if ever you still have standards to share I would very much appreciate it.