Cleanroom class in semiconductor

A

annnarumonp

Hi,

I'm working in semiconductor factory to do assembly and test IC product such as TQFP, FSBGA, TSSOP. Now encapsulant line (Mold line) was controlled as cleanroom class 10K and back end line was controlled class 100K. But I would like to propose to loose cleanroom class to be Mold line 100K and non-cleanroom for back end line.
1) Can I loose cleanroom class?
2) Do any standard to mention about cleanroom class of IC assemble?

I read thru ISO14644 and FED-STD-209E but it seem that they didn't specify the cleanroom class.

Pls help. Thanks.:confused:
Ann
 
E

e006823

Are you packaging devices in ceramic as well as plastic?

The back end of the line has always meant the assembly (packaging) and test part of the process to me. Is this what you mean as well?

Past experience has been that you need to maintain a clean room environment until after packaging. What that environment is depends on the cleanliness class of the devices manufactured (this should be in your customers documentation). I see no reason for the devices to be tested in a clean room.
 

Jen Kirley

Quality and Auditing Expert
Leader
Admin
My experience is that clean room requirements can be relaxed in the test stage because the chance for contaminants to enter the wafers' architecture has passed.

What remains is what's needed to make sure the tests are accurate and the product is not made less ready for release to customers. ESD and particulates at this stage may be concerns for not just product, but the test process integrity, so keep that in mind.

This was a very general, 20,000 foot altitude kind of response. I hope it helps!
 
Q

qualityboi

It depends on the product...we ahve run into problems with non-packaged wafer level products going to customer with contaminants from going to a class 1000 to 100000k...so I feel the best advice was given, go by what your data is telling you. Any problems with contamination at that level?

Also, If you are packing imaging products don't even think about it, protected with passivation, packaged, glass or whatever...customers want these clean...
 
A

annnarumonp

Thank you for all advise. My company changed the plan now. They don't want to loose cleanroom class anymore.

:thanx:
Ann
 

Al Rosen

Leader
Super Moderator
According to MIL-STD-883 Method 2010
Controlled environment. Shall be 1,000 (0.5 um or greater) particles/cubic foot controlled environment
(class 6 of ISO 14644-1), (see A.4.8.1.1.7 of appendix A of MIL-PRF-38535), except that the maximum allowable relative humidity shall not exceed 65 percent.
 
M

Murphys Law

I'm trying to think back to all my Assembly / test site visits and I believe they were all under clean room conditions up until mold.

Another reason you want to stick with a clean room is for hummidity control. You'd be susceptable to die cracks or warpage if too much hummidity gets in. I don't know how you'd control it in a non-clean room.

Molding is some way is at odd with a clean room. It is a dirty process (from a semiconductor geometry point of view) and you need to continually clean the mold shots. In fact, the probable source of particles being introduced would be residue carbonized mold from previous shots. As such it is a continuous opportunity for 5S in an assembly site. (Tip: run your finger along the top of the mold machine to see how dirty it is. That is source for airborne particles on the ICs).

Btw a side discussion on mold induced defects: From customer returns over the years, I've noticed PO (passivation oxide/overcoat) damage from mold compound particles tend to come from older wafer technologies. These are ones that have the topological metalization system. (This means that they go up and down with hills and trenches like the landscape.) When you get jagged mold filler particles, these act a stress point to puncture the PO/metalization through natural temp cycling.

The newer generation of IC's have a planar PO / metalization which means it is flat. Not only that but the PO is thicker. This combination of PO design does not present the point defect opportunities from mold compound filler particles that older PO technologies did.
 

millie6901

Registered Visitor
Hi,
my current control production cleanroom class 10k, for RH 30-60% and temperature 18-26°C (malaysia).
may i know any standard to refer are we compliance?
 
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