GMW3172 - Thermal Shock and PTC cycles required to validate an electronic system

E

Egabrum

#1
Hi,

I´m new to these forums, so I hope my question is not off-topic.

I´m trying to calculate the number of Thermal Shock + PTC cycles that are required to validate an electronic system according to GMW3172.

Apparently, the method is different in the revision of year 2004 (feb'04, I think) and in the one from dec'05.

In the latest version, there is an acceleration factor taking into account the ramp rate (ºC/min) in the Thermal Shock, based in the observations of Larry Edson.

The problem is that example on calculations in the appendix F seems to be wrong, but I don´t know if it is an error of calculation or an error in the formula.

Does anyone have experience in this subject?

Thanks
(I hope the question is not too specific...)
 
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