In IEC 62304, the assumption of 100% failure is used to determine the safety classification of the system (A, B or C), not for making decisions such as risk controls.
For PEMS (IEC 60601-1) there is no such assumption.
You could decide a single CPU is reliable. I found many such cases in practice. A CPU's hardware has to be super reliable for economic viability, so the failure rates for an individual logic bit, gate, memory cell are incredibly low. And even the rare case of CPU failure, the most common result is CPU lock-up, the risk of which is controlled by an external WDT, not by software.
Also, even if it is a single CPU, you would still have to use some monitoring software independent of the control software, such monitoring the feedback from an encoder on the motor. So from a software point of view, it is still a two channel system, control and protection.