IEC 60601 Creepage and Clearance Requirements on PCB

[AndrewJ]

I am developing a medical device that requires 60601 approvals which includes a device specific risk which requires mitigation by an electronic interlock circuit (requiring user intervention before the next action). Based on section 13 I understand that this interlock has to be single fault safe so I have two independent interlocks which prevent the harm from occurring.

Each interlock is constructed from analogue and digital logic at 3V and I am space constrained so I need to use small components and ICs with lead spacing less than 0.5mm. Section 13.2.1 of BS EN 60601-1:2006 + A12:2014 states that during the application of the single fault conditions the normal conditions identified in 8.1 a) also have to be applied. Where the spacing between two PCB tracks is less than 0.5mm they do not comply with the creepage distance requirements in table 16. Do I need to consider a short between tracks which don't comply with the creepage distance requirements as normal conditions when considering device specific hazards under single fault conditions? It is not clear whether a short in this situation has to be considered a normal condition when not being applied to electrical hazards.

I have just found that Annex A for subclause 13.1.1 states that the requirements for creepage and clearance are not intended to be required at the circuit board level (where the spacing cannot be compromised). This suggests that I do not have to consider shorting traces on a PCB as normal conditions but I cannot see how this is clearly referenced in the main standard. Based on this can two PCB traces separated by 0.3mm be exempt from having to be considered as shorted as normal conditions when applying single fault conditions?

Any help would be greatly appreciated.

 

[Pads38]

Hi Andrew and welcome to the forums.

The required creepage and clearance distances, as set out in section 8.9, are only required for insulations forming a MEANS OF PROTECTION. (Capitalisation indicates a defined term - see section 3). A MEANS OF PROTECTION (MOP) reduces the risk of electrical shock - it has a safety function.

For your insulation between PCB traces - that is functional insulation. There is no direct requirement in 60601 for minimum distances; you will need to rely on sound engineering judgement (I'm sure it's in a text book somewhere!). Factor in the 'pollution degree' ie the degradation over time due to contamination from dirt etc.

 

[Loekje]

I concur with PAD38.

We had a somewhat same situation where we actually did needed a MOP. This was resolved by applying conformal coating over parts of the traces and PCB. Mind though that it can be a real Pain in the Ass to proof that this coating is sufficient, in risk analysis and production control as well.

Lots of succes with your design,
Loek

 

[Pads38]

It is worth noting that if you use insulating compounds, such as conformal coating, you need then to apply the tests of section 8.9.3 to prove the suitability of your insulation.

This includes the thermal cycling test, which is both time consuming and very expensive to perform! And you can't really be sure of a positive outcome until you have done the test.

 

[Marc]

I can't speak to medical devices, but in aerospace when we did conformal coating or other "protection" we also had to do vibration, humidity and thermal shock testing. VERY expensive.

 

[AndrewJ]

Thank you all for your replies. I am trying to avoid conformal coating exactly because of the cost and testing time.

Loekje, I would be really interested to understand the situation where you did need a MOP. Can you share any more information?