Marking the material category for Component Terminal Finish (Jedec J-std-609)?

[Excelinda - 2010]

Belated happy Papa's Day to all father.

Just would like to know more about the requirements on marking and labelling
indicated at Jedec J-std-609. Since when it is required to mark the
material category for component terminal finish on the component and/or
container label? To which criteria does it applies?
I'm on a semicon. I just stumbled on this req'ts and i think we are not
yet updated here. Please help!

Thank you in advance to whatever information anybody can share.

Good afternoon po.

Em

 

[isabulg]

Hi Excelinda

Standard is valid since May 2007. The requirement is to distinguish leadfree products to other ones, and which category your product falls into (leaded/leadfree, using pure matte Sn or others ..)
So far, we are only using the Pb symbol on our labels, but not the interconnect definition (e0... e3).
Marking on the component itself can be very difficult (imagine on really small ICs ), that's why we decided to have it only on our outside package label.

This standard is to ease end-of life recycling ...

Good luck!