Re: Verification vs. Validation-what are the differences?
Susan,
I use a simple circuit board manufacturing example when I have to explain the difference between verification and validation.
In PCB manufacturing I ask:
1- Did you design for the right component to be at right location with correct polarity?
In circuit test (ICT) or inspection will verify those requirements...(Design verification)
2- Did the circuit board pass functional test? (Design Validation)
Hope this helps.
Sorry , but I have to disagree.
First off, you call your example as being from PCB manufacturing while in fact you refer to a PCB Assembly !
The right component being at the right location with the correct polarity is not a design verification, it is an inspection to verify that the assembly was done correctly (assembly vs. blueprint)
If it is intended as a design verification, it should be done before a board even exists through:
a)design review - verify that the schematics is correct (incl. calculations, simulations, etc)
b) layout vs. schematics
c) tests and measurements on breadboards , etc.
Functional test is definitely verification and not validation (assuming it is done on a first-off or small sample)
All of the above is done in a lab (room temperature)
Validation type activities (in your example) would be:
Functional testing over the entire specified temperature range (min. and max. specified temp)
Same as above with the board installed in the target application (rack, box or a mockup that would simulate surrounding thermal environment)
Testing that the board meets spec over the entire range of specified input voltages
EMI testing (immunity to RF radiation and emission meerting specified limits, when applicable)
Other environmental conditions (humidity, vibration, shock, etc. as and when applicable - think of a board for a laptop or mobile device- it may work perfectly in the lab but shatter to pieces when dropped on the floor).....and so on and on, depending on the intended functionality and use environment. There might be also regulatry issues involved. All of the latte are Validation.
To sum it up, design verification are all tests, inspections and analysis intended to verify that the design has the capability of performing its intended function.
Validation is to verify that this capability is maintained over the entire range of inputs, stresses, environmental conditions, regulatory and safety requirements and over production variability (tolerances0
Hope this clarifies the difference ...