Definition Verification vs. Validation - What are the differences?

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Marcelo

Inactive Registered Visitor
#12
It’s a shame that most people do not use ISO 9000:2005 even though ISO 9001, ISO/TS 16949 and AS9100 all state that this Standard is a normative reference and that the terms and definitions given in ISO 9000 apply (Clause 2 & 3).
I don´t think this is the real problem. In fact, the definitions of verification and validation in ISO 9000 are, in my point of view, veryyyyyyyy misleading.

The point is that the standards are no more thatn "best practices" taken from experience. In this way, i think that the real problem is a lack of understanding in engineering design, not the fact that the standards are not read.

Quality systems would be better if people would focus on what they do and how to do instead of wanting to fulfill the standards without knowing their background.

(and Susan this is not directed at you, it´s just a general commentary on my views of the field).
 
J

Jeff Frost

#14
It isn't reinforced as it should be and most of those same folks do not look upon the definitions and other material as applicable.........shame. In my case I don't interpret, I use the Standard.
I have learned over the years that many 2nd party auditors apply their own terms and definitions and then incorrectly say my organization in non-conformity to the requirements of the standard. We then educate them about terms and definitions and usually their finding of non-conformity is withdrawn.
 

BradM

Staff member
Admin
#15
Re: Verification vs. Validation-what are the differences?

Hmmm....to be perfectly honest...I'm not really sure!:biglaugh:
I guess I"m just struggling with the entire design concept. When we took the manufacturing company in as a division of our company, we took their designs and drawings and made them our own. But, since we're manufacturing, I was told that we do need to include 7.3 in our QMS. I hope this makes sense...I'm starting to confuse myself!
You know what? That's an excellent and perfectly honest answer. Hence, the reason why I ask the question:tg: Please... you are in the same boat with many of us. If you see how many threads there are on the subject, you see that we all get caught up in terminology.

Several here have provided some good advice. Randy's reference to the standard may be a good place to develop a baseline of understanding for you and your organization.
 

michellemmm

Quest For Quality
#19
Re: Verification vs. Validation-what are the differences?

Hmmm....to be perfectly honest...I'm not really sure!:biglaugh:
I guess I"m just struggling with the entire design concept. When we took the manufacturing company in as a division of our company, we took their designs and drawings and made them our own. But, since we're manufacturing, I was told that we do need to include 7.3 in our QMS. I hope this makes sense...I'm starting to confuse myself!
Susan,
I use a simple circuit board manufacturing example when I have to explain the difference between verification and validation.

In PCB manufacturing I ask:

1- Did you design for the right component to be at right location with correct polarity?
In circuit test (ICT) or inspection will verify those requirements...(Design verification)

2- Did the circuit board pass functional test? (Design Validation)

Hope this helps.
 
W

w_grunfeld

#20
Re: Verification vs. Validation-what are the differences?

Susan,
I use a simple circuit board manufacturing example when I have to explain the difference between verification and validation.

In PCB manufacturing I ask:

1- Did you design for the right component to be at right location with correct polarity?
In circuit test (ICT) or inspection will verify those requirements...(Design verification)

2- Did the circuit board pass functional test? (Design Validation)

Hope this helps.
Sorry , but I have to disagree.
First off, you call your example as being from PCB manufacturing while in fact you refer to a PCB Assembly !
The right component being at the right location with the correct polarity is not a design verification, it is an inspection to verify that the assembly was done correctly (assembly vs. blueprint)
If it is intended as a design verification, it should be done before a board even exists through:
a)design review - verify that the schematics is correct (incl. calculations, simulations, etc)
b) layout vs. schematics
c) tests and measurements on breadboards , etc.
Functional test is definitely verification and not validation (assuming it is done on a first-off or small sample)
All of the above is done in a lab (room temperature)
Validation type activities (in your example) would be:
Functional testing over the entire specified temperature range (min. and max. specified temp)
Same as above with the board installed in the target application (rack, box or a mockup that would simulate surrounding thermal environment)
Testing that the board meets spec over the entire range of specified input voltages
EMI testing (immunity to RF radiation and emission meerting specified limits, when applicable)
Other environmental conditions (humidity, vibration, shock, etc. as and when applicable - think of a board for a laptop or mobile device- it may work perfectly in the lab but shatter to pieces when dropped on the floor).....and so on and on, depending on the intended functionality and use environment. There might be also regulatry issues involved. All of the latte are Validation.
To sum it up, design verification are all tests, inspections and analysis intended to verify that the design has the capability of performing its intended function.
Validation is to verify that this capability is maintained over the entire range of inputs, stresses, environmental conditions, regulatory and safety requirements and over production variability (tolerances0
Hope this clarifies the difference ...
 
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