A
andypatkinson
Hi,
Can anyone provide a mapping of IEC 62304 artefacts (SRS, SAD, etc) to the 820.30 phases: Planning, Design Input, Device Design, Design Output, Verification, Validation, Design Review.
(As a side note, I cannot even find a good definition of what 'Design' means when considering 820.30 Design Controls and medical device software development - any thoughts, interpretations, suggestions?)
I have seen so many contradictory and incorrect answers,
the favourite being:
Planning: SDP
Design Input: System Requirements, Medical Device Risk Assessment, SRS
Device Design: SAD, SDD, Code
Design Output: Release Notes, Binary
Verification: Verification Report
What say you learned folk?
TIA
Andy
Can anyone provide a mapping of IEC 62304 artefacts (SRS, SAD, etc) to the 820.30 phases: Planning, Design Input, Device Design, Design Output, Verification, Validation, Design Review.
(As a side note, I cannot even find a good definition of what 'Design' means when considering 820.30 Design Controls and medical device software development - any thoughts, interpretations, suggestions?)
I have seen so many contradictory and incorrect answers,
the favourite being:
Planning: SDP
Design Input: System Requirements, Medical Device Risk Assessment, SRS
Device Design: SAD, SDD, Code
Design Output: Release Notes, Binary
Verification: Verification Report
What say you learned folk?
TIA
Andy